The invention relates generally to the formation of integrated circuit devices and more particularly to a process for enhancing refresh in Dynamic Random Access Memory devices (DRAMs).
Generally, integrated circuits are mass produced by forming many identical circuit patterns on a single silicon wafer, which is thereafter cut into many identical dies or xe2x80x9cchips.xe2x80x9d Integrated circuits, also commonly referred to as semiconductor devices, are made of various materials that may be electrically conductive, electrically nonconductive (insulators) or electrically semiconductive. Silicon, in single crystal or polycrystalline form, is the most commonly used semiconductor material. Both forms of silicon can be made electrically conductive by adding impurities. The introduction of impurities into silicon is commonly referred to as doping. Silicon is typically doped with boron or phosphorus. Boron atoms have one less valence electron than silicon atoms. Therefore, if the silicon is doped with boron, then electron xe2x80x9cholesxe2x80x9d become the dominant charge carrier and the doped silicon is referred to as p-type silicon. By contrast, phosphorous atoms have one more valence electron than silicon atoms. If the silicon is doped with phosphorous, then electrons become the dominant charge carriers and the doped silicon is referred to as n-type silicon.
Dynamic Random Access Memory devices (DRAMs) comprise arrays of memory cells which contain two basic componentsxe2x80x94a field effect access transistor and a capacitor. Typically, one side of the transistor is connected to one side of the capacitor. This connection is made between a capacitor bottom electrode and an active area. The areas in a DRAM in which electrical connections are made are generally referred to as active areas. Active areas consist of discrete specially doped regions in the surface of the silicon substrate which serve as electrical contact points (or xe2x80x9cburied contactsxe2x80x9d) as well as source/drain regions for the access transistor. The other side of the transistor and the transistor gate electrode are connected to external contactsxe2x80x94a bit line and a word line, respectively. The other side of the capacitor, the capacitor top electrode, is connected to a reference voltage. Therefore, the formation of the DRAM memory cell comprises the formation of a transistor, a capacitor, a connection between the capacitor and the transistor, and contacts to external circuits.
The many advantages of the formation of smaller circuit components, so that more and more memory cells may be packed onto each chip, are well known. One such advantage of miniaturization of cell components, and the corresponding reduction in memory cell spacing, is that the operating voltages for the DRAM may be decreased. Thus, the cost to operate the device is reduced and its reliability and longevity is enhanced.
Lower operating voltages, however, reduce the time within which each memory cell must be recharged or xe2x80x9crefreshedxe2x80x9d because less charge is stored on the cell. In DRAMs, the charge on each memory cell must be refreshed periodically because the cell loses or xe2x80x9cleaksxe2x80x9d charge through the junctions between areas within the silicon substrate having different doping/conductivity characteristics. If the cell is not refreshed before losing a threshold level of charge, then the cell will fail, i.e., lose the bit of information stored therein. And, if a cell fails, then the chip itself is defective and cannot be used. The rate at which charge is leaked through these junctions is an important factor in determining refresh timexe2x80x94the time within which each cell must be recharged. Consequently, it is advantageous to minimize junction leakage to increase refresh time and help compensate for the reductions in refresh time caused by lower operating voltages.
Improvements in refresh are also needed to compensate for increased packing densities and refresh degradation associated with contact misalignment. As more and more cells are packed onto each chip, more time is required to refresh all of the cells on the chip. Further, increased packing densities and corresponding cell miniaturization increases refresh degradation due to trap assisted tunneling, micro zenering and other such refresh loss mechanisms. Since refresh time is controlled by the weakest cell, the average refresh for all cells must be increased to keep the weakest cell above the minimum threshold. There is, thus, a need to enhance refresh to lessen or eliminate the effects of these loss mechanisms and otherwise provide for sufficient time within which all cells on the chip may be refreshed.
Refresh degradation has been observed when contact corridors are misaligned to the active areas. As the size of the memory cell is reduced, the size of the active areas and the corridors available for the capacitor bottom electrodes to reach those active areas are also reduced. Hence, proper alignment of the contacts formed in these corridors becomes more difficult.
One approach to a solution for the problem of obtaining proper contact alignment in narrow contact corridors is the use of an etch stop layer or similar structure to control the corridor etch. One such process of forming contacts is disclosed in U.S. Pat. No. 5,292,677, issued to Dennison on Mar. 8, 1994. Dennison describes a DRAM formation process using an etch stop layer to self-align the contact corridors to the transistor gate and word lines, and corresponding active areas in the substrate. Although this process substantially reduces the risk of contact misalignment and, incidentally, may lessen refresh degradation associated therewith, it does not address refresh problems associated with lower operating voltages or junction leakage.
Another approach to the problem of contact misalignment is illustrated in U.S. Pat. No. 4,512,073, issued to Hsu on Apr. 23, 1985. Hsu describes a process for precluding a metal contact from short circuiting the doped regions to the substrate and for preventing the xe2x80x9cspikingxe2x80x9d of a metal contact through the doped region. In Hsu, phosphorous is implanted into the previously doped active areas to dope that portion of the substrate that may have been exposed due to misalignment of the contact corridor. As with the Dennison patent, Hsu does not address the problems of refresh degradation in general, and specifically with regard to refresh degradation associated with junction leakage, lower device operating voltages, and misalignment of the contact between the polysilicon capacitor bottom electrode and the transistor source/drain.
There is a need for a DRAM fabrication process that minimizes the problems of refresh degradation associated with miniaturization of cell components and decreased operating voltages, as well as refresh degradation that may result from contact misalignment and junction leakage.
One object of the invention is to enhance refresh in dynamic access memory devices.
Another object is to alleviate refresh degradation associated with the miniaturization of memory cell components and decreased operating voltages.
Another object is to lessen the adverse effect that contact misalignment and junction leakage may have on refresh.
According to the present invention, these and other objects are achieved by a process of implanting impurities into (i.e., doping) the capacitor buried contact after formation of the access transistor components. The process comprises forming a gate insulating layer on a substrate and a transistor gate electrode on the gate insulating layer. First and second transistor source/drain regions are formed on the substrate adjacent to each side of the gate electrodes. Impurities are then implanted into the first source/drain region which will serve as the capacitor buried contact. If the starting material for the substrate is p-type silicon, then n-type impurities will be implanted into the source/drain region.
In another aspect of the invention, the n-type impurities are phosphorous atoms. The phosphorous ions are implanted at an implantation energy level up to 200 KeV to a depth of approximately 500-2000 angstroms.
In another aspect of the invention, a capacitor first (or bottom) conductor, made of doped polysilicon, is formed to contact the source/drain region after the phosphorous implant. Then, a dielectric layer is formed over the first conductor and a polysilicon second conductor is formed over the dielectric layer. The memory cell may be completed by forming an insulating layer over the structure previously formed, patterning and etching the insulating layer and continuing to etch down to expose portions of the second source/drain region and, thereafter, forming a metal bit line contact contacting the exposed second source/drain region.
The process of the invention, implanting impurities into the capacitor buried contact after formation of the source/drain regions, thus enhances refresh of the memory cell by, it is believed, eliminating one or more defects in the cell.
Additional objects, advantages and novel features of the invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.